Electrical Engineering and Computer Science
SUN/Synopsys Charles Babbage Computing Lab
Established in September 2005, with the Charles Babbage Grant
and SUN Microsystems
, this lab is equipped with 30 Sun Ray 170 ultra-thin clients loaded with 50 Synopsys EDA (Electronic Design Automation) University Tool Package software and licenses. Syracuse University is among the first universities to receive this grant. This modern computing facility with the most comprehensive set of EDA tools, located in the Center for Science and Technology, is being used in numerous undergraduate and graduate courses as well as several research projects using a variety of EDA tools.
Synopsys University Courseware
SU has actively participated in developing Synopsys University Courseware
, for which a course, Introduction to Logic Design
, had been developed at SU. This is a digital design course which will help students in understanding the basic concepts of high level digital design using hardware description languages and Synopsys (design automation) tools. Some of the topics include: Number systems and codes; Digital electronics; Combinational logic design principles and practices; Introduction to sequential logic design; High level digital design using design automation tools. This and other courses are accessible through a secure online membership at Synopsys SolvNet
Teaching at SU with Synopsys Tools
tools from Design Vision and System Studio to Physical Compiler and Hspice at Charles Babbage Computing Lab are used in the following classes at SU:
CSE 261 – Digital Logic Design:
Number representations, Boolean algebra, logic minimization, memory circuits, counters, state diagrams, state machine design, arithmetic circuits, and asynchronous circuits. Logic simulators will be used to demonstrate and provide students with design activities.
CSE 381 – Computer Architecture:
Data representation, memory hierarchies, protection, specialized processors, multiple computers, performance evaluation, and reliability.
CSE 471 – Introduction to Embedded System Design:
Systematic design of embedded systems: System specification and architecture modeling. Components of embedded systems: CPU, ASIC, control systems, interfacing peripherals. Embedded computing platforms and real-time operating systems.
CSE 561 – Digital Machine Design:
Behavioral and structural design methods and examples using a hardware description language. Control, arithmetic, bus systems, memory systems. Logic synthesis from hardware language descriptions.
CSE 565 – Digital Design Test and Verification:
Techniques for validating the correctness of the logical and physical implementation of a digital system in two independent modules: (1) functional verification, and (2) test and validation.
CSE 661 – Advanced Computer Architecture:
Advanced computer architecture including discussion of instruction set design (RISC and CISC), virtual memory system design, memory hierarchies, cache memories, pipelining, vector processing, I/O subsystems, co-processors, and multiprocessor architectures. Case studies of current systems.
CSE 671 – Embedded System Design:
Methodologies for systematic design of embedded systems. System specification, architecture modeling, component partitioning, estimation metrics, hardware software co-design. Embedded computing platforms and programming. Putting it all together: ASIC, CPU, and glue logic. Individual project required.
CSE 772 – Testing of Digital Circuits:
Physical circuit failures and fault models. Test generation algorithms. Fault simulation and fault coverage. Random pattern testing. Sequential circuit testing. Test application and response processing techniques. Memory, PLA and function testing. Design for testability.
Current Research Projects Using Synopsys Tools
SystemC Implementation of the IEEE 1588 Clock Synchronization Protocol:
This project is undertaken for Lockheed Martin. The main goal of this project is to implement the IEEE 1588 clock synchronization protocol into an ALTERA FPGA from system level specifications using SystemC with Synopsys CoCentric SystemC Complier. An accuracy of less than 50ns will be needed for the synchronization. Optimization of the SystemC code, such as better performance gets achieved, will be an important goal in this project. Also, implementation of heterogeneous systems form System level specifications is a secondary goal of this project.